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LOW SKEW, 1-TO-22 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
ICS8534-01
General Description
The ICS8534-01 is a low skew, 1-to-22 Differential-to-3.3V LVPECL Fanout Buffer and a HiPerClockSTM member of the HiPerClockSTM Family of High Performance Clock Solutions from IDT. The ICS8534-01 has two selectable clock inputs. The CLK, nCLK pair can accept most standard differential input levels. The PCLK, nPCLK pair can accept LVPECL, CML, or SSTL input levels. The device is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the OE pin. The ICS8534-01's low output and part-to-part skew characteristics make it ideal for workstation, server, and other high performance clock distribution applications.
Features
* * * * * * * * * * *
Twenty-two differential LVPECL outputs Selectable differential CLK/nCLK or LVPECL clock inputs can accept the following differential input levels: LVDS, LVPECL, LVHSTL CLK/nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL PCLK/nPCLK supports the following input levels: LVPECL, CML, SSTL Maximum output frequency: 500MHz Output skew: 100ps (maximum) Translates any single-ended input signal (LVCMOS, LVTTL, GTL) to LVPECL levels with resistor bias on nCLK input Additive phase jitter, RMS): 0.04ps (typical) Full 3.3V supply mode 0C to 85C ambient operating temperature Available in both standard (RoHS 5) and lead-free (RoHS 6) packages.
ICS
Block Diagram
CLK_SEL
Pullup
Pin Assignment
QC11 nQ11 Q12 nQ12 Q13 nQ13 Q8 nQ8 Q9 nQ9 Q10 nQ10 VCCO Q7 nQ7 VCCO
CLK Pulldown nCLK Pullup/Pulldown PCLK Pulldown nPCLK Pullup/Pulldown OE
Pullup
0 1 LE Q D
22
Q0:Q21 22 nQ0:nQ21
VCCO nQ6 Q6 nQ5 Q5 nQ4 Q4 nQ3 Q3 nQ2 Q2 nQ1 Q1 nQ0 Q0 VCCO
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 3 46 4 45 5 44 6 43 7 42 8 41 9 40 10 39 11 38 12 37 13 36 14 35 1 2
VCCO Q14 nQ14 Q15 nQ15 Q16 nQ16 Q17 nQ17 Q18 nQ18 Q19 nQ19 Q20 nQ20 VCCO
ICS8534-01
15 34 16 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
VCCO nc nc VCC CLK nCLK CLK_SEL PCLK nPCLK VEE OE nc nc nQ21 Q21 VCCO
64-Lead TQFP E-Pad 10mm x 10mm x 1.0mm package body Y package Top View
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Table 1. Pin Descriptions
Number 1, 16, 17, 32, 33, 48, 49, 64 2, 3, 12, 13 4 5 6 7 8 9 10 11 14, 15 18, 19 20, 21 22, 23 24, 25 26, 27 28, 29 30, 31 34, 35 36, 37 38, 39 40, 41 42, 43 44, 45 46, 47 50, 51 52, 53 54, 55 56, 57 58, 59 60, 61 59 Name VCCO nc VCC CLK nCLK CLK_SEL PCLK nPCLK VEE OE nQ21, Q21 nQ20, Q20 nQ19, Q19 nQ18, Q18 nQ17, Q17 nQ16, Q16 nQ15, Q15 nQ14, Q14 nQ13, Q13 nQ12, Q12 nQ11, Q11 nQ10, Q10 nQ9, Q9 nQ8, Q8 nQ7, Q7 nQ6, Q6 nQ5, Q5 nQ4, Q4 nQ3, Q3 nQ2, Q2 nQ1, Q1 nQ0, Q0 Power Unused Power Input Input Input Input Input Power Input Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Pullup Pulldown Pullup/ Pulldown Pullup Pulldown Pullup/ Pulldown Type Description Output supply pins for LVPECL outputs. No connect. Core supply pin for LVPECL outputs. Non-inverting differential clock input. Inverting differential clock input. Pulled to 2/3 VCC. Clock select input. When HIGH, selects PCLK, nPCLK inputs. When LOW, selects CLK, nCLK inputs. LVCMOS / LVTTL interface levels. Non-inverting differential LVPECL clock input. Inverting differential LVPECL clock input. Pulled to 2/3 VCC. Negative supply pin. Output enable. When logic HIGH, the outputs are enabled (default). When logic LOW, the outputs are disabled and drive differential low: Qx = LOW, nQx = HIGH. LVCMOS / LVTTL interface levels. Differential clock outputs. LVPECL interface Levels. Differential clock outputs. LVPECL interface Levels. Differential clock outputs. LVPECL interface Levels. Differential clock outputs. LVPECL interface Levels. Differential clock outputs. LVPECL interface Levels. Differential clock outputs. LVPECL interface Levels. Differential clock outputs. LVPECL interface Levels. Differential clock outputs. LVPECL interface Levels. Differential clock outputs. LVPECL interface Levels. Differential clock outputs. LVPECL interface Levels. Differential clock outputs. LVPECL interface Levels. Differential clock outputs. LVPECL interface Levels. Differential clock outputs. LVPECL interface Levels. Differential clock outputs. LVPECL interface Levels. Differential clock outputs. LVPECL interface Levels. Differential clock outputs. LVPECL interface Levels. Differential clock outputs. LVPECL interface Levels. Differential clock outputs. LVPECL interface Levels. Differential clock outputs. LVPECL interface Levels. Differential clock outputs. LVPECL interface Levels. Differential clock outputs. LVPECL interface Levels. Differential clock outputs. LVPECL interface Levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
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Table 2. Pin Characteristics
Symbol CIN RPULLUP RPULLDOWN Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Test Conditions Minimum Typical 4 37 75 Maximum Units pF k k
Function Table
Table 3. Control Input Function Table.
Inputs OE 0 0 1 1 CLK_SEL 0 1 0 1 Outputs Q0:Q21 LOW LOW CLK PCLK nQ0:nQ21 HIGH HIGH nCLK nPCLK
Disabled
Enabled
nCLK, nPCLK CLK, PCLK
OE
nQ0:nQ21 Q0:Q21
Figure 1. OE Timing Diagram
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Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Supply Voltage, VCC Inputs, VI Outputs, IO (LVPECL) Continuous Current Surge Current Package Thermal Impedance, JA Storage Temperature, TSTG Rating 4.6V -0.5V to VCC + 0.5V 50mA 100mA 22.3C/W (0 lfpm) -65C to 150C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, VCC = VCCO = 3.3V 5%, VEE = 0V, TA = 0C to 85C
Symbol VCC VCCO IEE Parameter Core Supply Voltage Output Supply Voltage Power Supply Current Test Conditions Minimum 3.135 3.135 Typical 3.3 3.3 Maximum 3.465 3.465 230 Units V V mA
Table 4B. LVCMOS/LVTTL DC Characteristics, VCC = VCCO = 3.3V 5%, VEE = 0V, TA = 0C to 85C
Symbol VIH VIL IIH IIL Parameter Input High Voltage Input Low Voltage Input High Current Input Low Current OE, CLK_SEL OE, CLK_SEL VCC = VIN = 3.465V VCC = 3.465V, VIN = 0V -150 Test Conditions Minimum 2 -0.3 Typical Maximum VCC + 0.3 0.8 5 Units V V A A
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Table 4C. Differential DC Characteristics, VCC = VCCO = 3.3V 5%, VEE = 0V, TA = 0C to 85C
Symbol IIH Parameter CLK Input High Current nCLK CLK IIL VPP VCMR Input Low Current nCLK Peak-to-Peak Voltage; NOTE 1 Common Mode Input Voltage; NOTE 1, 2 Test Conditions VCC = VIN = 3.465V VCC = VIN = 3.465V VCC = 3.465V, VIN = 0V VCC = 3.465V, VIN = 0V -5 -150 0.15 VEE + 0.5 1.3 VCC - 0.85 Minimum Typical Maximum 150 5 Units A A A A V V
NOTE 1: VIL should not be less than -0.3V. NOTE 2: Common mode input voltage is defined as VIH.
Table 4C. LVPECL DC Characteristics, VCC = VCCO = 3.3V 5%, VEE = 0V, TA = 0C to 85C
Symbol IIH Parameter PCLK Input High Current nPCLK PCLK IIL VPP VCMR VOH VOL VSWING Input Low Current nPCLK Peak-to-Peak Voltage; NOTE 1 Common Mode Input Voltage; NOTE 1, 2 Output High Voltage; NOTE 3 Output Low Voltage; NOTE 3 Peak-to-Peak Output Voltage Swing Test Conditions VCC = VIN = 3.465V VCC = VIN = 3.465V VCC = 3.465V, VIN = 0V VCC = 3.465V, VIN = 0V -5 -150 0.3 VEE + 1.5 VCCO - 1.4 VCCO - 2.0 0.6 1.0 VCC VCCO - 0.9 VCCO - 1.7 1.0 Minimum Typical Maximum 150 5 Units A A A A V V V V V
NOTE 1: VIL should not be less than -0.3V. NOTE 2: Common mode input voltage is defined as VIH. NOTE 3: Outputs terminated with 50 to VCCO - 2V.
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AC Electrical Characteristics
Table 5. VCC = VCCO = 3.3V 5%, VEE = 0V, TA = 0C to 85C
Symbol fMAX tPD tsk(o) tsk(pp) tjit tR / tF tS tH odc Parameter Output Frequency Propagation Delay; NOTE 1 Output Skew; NOTE 2, 3 Part-to-Part Skew; NOTE 3, 4 Buffer Additive Phase Jitter, RMS, refer to Additive Phase Jitter section; NOTE 5 Output Rise/ Fall Time Setup Time Hold Time Output Duty Cycle 266MHz 266 < 500MHz Integration Range: 12kHz - 20MHz 20% to 80% 200 1 0.5 48 46 52 54 0.4 700 500MHz 2.0 Test Conditions Minimum Typical Maximum 500 3.0 100 700 Units MHz ns ps ps ps ps ns ns % %
All parameters measured at fMAX unless noted otherwise. Special thermal considerations may be required. See Applications Section. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. Measured at the output differential cross points. NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions at the same temperature. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 5: Driving only one input clock.
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Additive Phase Jitter
The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in the 1Hz band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot.
0 -10 -20 -30 -40 -50 -60
Additive Phase Jitter, RMS @ 156.25MHz 12kHz to 20MHz = 0.04ps (typical)
SSB Phase Noise dBc/Hz
-70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 1k 10k 100k 1M 10M 100M
Offset Frequency (Hz)
As with most timing specifications, phase noise measurements has issues relating to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the
device. This is illustrated above. The device meets the noise floor of what is shown, but can actually be lower. The phase noise is dependant on the input source and measurement equipment.
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Parameter Measurement Information
2V
VCC
VCC, VCCO
Qx
SCOPE
nCLK, nPCLK
V
PP
Cross Points
V
CMR
CLK, PCLK
LVPECL
nQx VEE
VEE
-1.3V 0.165V
3.3V LVPECL Output Load AC Test Circuit
Differential Input Level
nQx Qx
Par t 1
nQx Qx
nQy Qy
Par t 2
nQy Qy
tsk(pp)
tsk(o)
Part-to-Part Skew
Output Skew
nCLK, nPCLK CLK, PCLK nQ0:nQ21 Q0:Q21
80% Clock Outputs
tPD
80% VSW I N G
20% tR tF
20%
Propagation Delay
Output Rise/Fall Time
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Parameter Measurement Information, continued
nQ0:nQ21 Q0:Q21
t PW
t
PERIOD
odc =
t PW t PERIOD
x 100%
-
Output Duty Cycle/Pulse Width/Period
Application Information
Wiring the Differential Input to Accept Single Ended Levels
Figure 2 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VCC/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
VCC
R1 1K Single Ended Clock Input CLK, PCLK nCLK. nPCLK
V_REF
C1 0.1u
R2 1K
Figure 2. Single-Ended Signal Driving Differential Input
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Differential Clock Input Interface
The CLK /nCLK accepts LVPECL, LVDS, LVHSTL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 3A to 3F show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confirm the driver termination requirements.
3.3V 3.3V 3.3V 3.3V R1 50 Zo = 50 CLK Zo = 50 nCLK Zo = 50 R1 100 nCLK R2 50 3.3V Zo = 50
CLK
CML
HiPerClockS
CML Built-In Pullup
HiPerClockS
Figure 3A. HiPerClockS CLK/nCLK Input Driven by an IDT Open Collector CML Driver
Figure 3B. HiPerClockS CLK/nCLK Input Driven by a Built-In Pullup CML Driver
3.3V 3.3V 3.3V R3 125 Zo = 50 CLK Zo = 50 nCLK Zo = 50 C2 nCLK R4 125 3.3V 3.3V
3.3V LVPECL
Zo = 50
C1 CLK
LVPECL
R1 84 R2 84
HiPerClockS
R5 100 - 200 R6 100 - 200 R1 125 R2 125
HiPerClockS
Figure 3C. HiPerClockS CLK/nCLK Input Driven by a 3.3V LVPECL Driver
2.5V 3.3V 2.5V R3 120 Zo = 60 CLK R4 120
Figure 3D. HiPerClockS CLK/nCLK Input Driven by a 3.3V LVPECL Driver with AC Couple
3.3V 3.3V Zo = 50
CLK Zo = 60 nCLK R1 100
SSTL
R1 120 R2 120
HiPerClockS LVDS
Zo = 50
nCLK
HiPerClockS
Figure 3E. HiPerClockS CLK/nCLK Input Driven by an SSTL Driver
Figure 3F. HiPerClockS CLK/nCLK Input Driven by a 3.3V LVDS Driver
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LVPECL Clock Input Interface
The PCLK /nPCLK accepts LVPECL, CML, SSTL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 4A to 4F show interface examples for the HiPerClockS PCLK/nPCLK input driven by the most common driver types. The input interfaces suggested here are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confirm the driver termination requirements.
3.3V 3.3V 3.3V 3.3V R1 50 Zo = 50 PCLK Zo = 50 nPCLK Zo = 50 R1 100 nPCLK R2 50 3.3V Zo = 50
PCLK
CML
HiPerClockS PCLK/nPCLK
CML Built-In Pullup
HiPerClockS PCLK/nPCLK
Figure 4A. HiPerClockS PCLK/nPCLK Input Driven by an Open Collector CML Driver
Figure 4B. HiPerClockS PCLK/nPCLK Input Driven by a Built-In Pullup CML Driver
3.3V 3.3V 3.3V R3 125 Zo = 50 PCLK Zo = 50 nPCLK R4 125
3.3V 3.3V 3.3V R3 84 Zo = 50 C1 PCLK Zo = 50 C2 nPCLK R4 84
3.3V LVPECL
LVPECL
R1 84 R2 84
HiPerClockS Input
R5 100 - 200
R6 100 - 200
R1 125
R2 125
HiPerClockS PCLK/nPCLK
Figure 4C. HiPerClockS PCLK/nPCLK Input Driven by a 3.3V LVPECL Driver
Figure 4D. HiPerClockS PCLK/nPCLK Input Driven by a 3.3V LVPECL Driver with AC Couple
2.5V 3.3V 2.5V R3 120 Zo = 60 PCLK Zo = 60 nPCLK Zo = 50 R5 100 C2 R4 120 3.3V Zo = 50 C1
3.3V 3.3V R3 1k R4 1k PCLK
nPCLK R1 1k R2 1k
SSTL
R1 120 R2 120
HiPerClockS PCLK/nPCLK
LVDS
HiPerClockS PCLK/nPCLK
Figure 4E. HiPerClockS PCLK/nPCLK Input Driven by an SSTL Driver (delete this figure
Figure 4F. HiPerClockS PCLK/nPCLK Input Driven by a 3.3V LVDS Driver
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Recommendations for Unused Input and Output Pins
Inputs: CLK/nCLK Inputs
For applications not requiring the use of the differential input, both CLK and nCLK can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from CLK to ground.
Outputs: LVPECL Outputs
All unused LVPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated.
PCLK/nPCLK Inputs
For applications not requiring the use of the differential input, both PCLK and nPCLK can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from PCLK to ground.
LVCMOS Control Pins
All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1k resistor can be used.
Termination for 3.3V LVPECL Outputs
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 5A and 5B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations.
3.3V Zo = 50 125 FOUT FIN Zo = 50 FOUT 50 1 Z ((VOH + VOL) / (VCC - 2)) - 2 o 50 VCC - 2V RTT Zo = 50 84 84 FIN 125
Zo = 50
RTT =
Figure 5A. 3.3V LVPECL Output Termination
Figure 5B. 3.3V LVPECL Output Termination
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EPAD Thermal Release Path
In order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the Printed Circuit Board (PCB) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in Figure 6. The solderable area on the PCB, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. Sufficient clearance should be designed on the PCB between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. While the land pattern on the PCB provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are necessary to effectively conduct from the surface of the PCB to the ground plane(s). The land pattern must be connected to ground through these vias. The vias act as "heat pipes". The number of vias (i.e. "heat pipes") are application specific and dependent upon the package power dissipation as well as electrical conductivity requirements. Thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. Maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. It is recommended to use as many vias connected to ground as possible. It is also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug and the thermal land. Precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. Note: These recommendations are to be used as a guideline only. For further information, refer to the Application Note on the Surface Mount Assembly of Amkor's Thermally/Electrically Enhance Leadfame Base Package, Amkor Technology.
SOLDER PIN EXPOSED HEAT SLUG
SOLDER
PIN
SOLDER
PIN PAD
GROUND PLANE THERMAL VIA
LAND PATTERN (GROUND PAD)
PIN PAD
Figure 6. Assembly for Exposed Pad Thermal Release Path - Side View (drawing not to scale)
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Power Considerations
This section provides information on power dissipation and junction temperature for the ICS5334-01. Equations and example calculations are also provided.
1.
Power Dissipation.
The total power dissipation for the ICS534-01 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. * * Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 230mA = 796.95mW Power (outputs)MAX = 30mW/Loaded Output pair If all outputs are loaded, the total power is 22 * 30mW = 660mW
Total Power_MAX (3.8V, with all outputs switching) = 796.95mW + 660mW = 153.08mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockS devices is 125C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming 0 air flow and a multi-layer board, the appropriate value is 17.2C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85C with all outputs switching is: 85C + 1.457W * 17.2C/W = 110.1C. This is below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (single layer or multi-layer).
Table 6. Thermal Resistance JA for 64 Lead TQFP, Forced Convection
JA by Velocity Linear Feet per Minute Multi-Layer PCB, JEDEC Standard Test Boards 0 22.3C/W 200 17.2C/W 500 15.1C/W
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3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 7.
VCCO
Q1
VOUT
RL 50
VCCO - 2V
Figure 7. LVPECL Driver Circuit and Termination
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of VCCO - 2V.
* * For logic high, VOUT = VOH_MAX = VCCO_MAX - 0.9V (VCCO_MAX - VOH_MAX) = 0.9V For logic low, VOUT = VOL_MAX = VCCO_MAX - 1.7V (VCCO_MAX - VOL_MAX) = 1.7V
Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low.
Pd_H = [(VOH_MAX - (VCCO_MAX - 2V))/RL] * (VCCO_MAX - VOH_MAX) = [(2V - (VCCO_MAX - VOH_MAX))/RL] * (VCCO_MAX - VOH_MAX) = [(2V - 0.9V)/50] * 0.9V = 19.8mW
Pd_L = [(VOL_MAX - (VCCO_MAX - 2V))/RL] * (VCCO_MAX - VOL_MAX) = [(2V - (VCCO_MAX - VOL_MAX))/RL] * (VCCO_MAX - VOL_MAX) = [(2V - 1.7V)/50] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
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Reliability Information
Table 7. JA vs. Air Flow Table for a 64 Lead TQFP, E-Pad
JA vs. Air Flow Linear Feet per Minute Multi-Layer PCB, JEDEC Standard Test Boards 0 22.3C/W 200 17.2C/W 500 15.1C/W
Transistor Count
The transistor count for ICS8534-01 is: 1474
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Package Outline and Package Dimension
Package Outline - Y Suffix for 64 Lead TQFP, E-Pad
-HD VERSION EXPOSED PAD DOWN
Table 8. Package Dimensions for 64 Lead TQFP, E-Pad
JEDEC Variation: ACD All Dimensions in Millimeters Minimum Nominal Maximum 64 1.20 0.05 0.10 0.15 0.95 1.00 1.05 0.17 0.22 0.27 0.09 0.20 12.00 Basic 10.00 Basic 7.50 Ref. 4.5 5.0 5.5 0.50 Basic 0.45 0.60 0.75 0 7 0.08
Symbol N A A1 A2 b c D&E D1 & E1 D2 & E2 D3 & E3 e L ccc
Reference Document: JEDEC Publication 95, MS-026
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Ordering Information
Table 9. Ordering Information Part/Order Number Marking Package Shipping Packaging Temperature ICS8534AY-01 ICS8534AY-01 64 Lead TQFP Tray 0C to +85C ICS8534AY-01T ICS8534AY-01 64 Lead TQFP 500 Tape & Reel 0C to +85C ICS8534AY-01LF ICS8534AY-01LF "Lead-Free" 64 Lead TQFP Tray 0C to +85C ICS8534AY-01LFT ICS8534AY-01LF "Lead-Free" 64 Lead TQFP 500 Tape & Reel 0C to +85C NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications, such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
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Revision History Sheet
Rev A Table Page 15 1 12 13 18 Description of Change Updated Package Outline and Package Dimensions. Features Section - added lead-free bullet. Added Recommendations for Unused Input and Output Pins section. Updated EPad Thermal Release Path section. Ordering Information Table. Added lead-free part number, marking and note. Updated format throughout the datasheet. Date 11/19/04
A
T9
12/06/07
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